An integrated circuit is a network of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), metal-oxide-semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), thin-film transistors (TFT), etc.
The development of complicated integrated circuits often requires the use of powerful numerical simulation programs. For example, circuit simulation is an essential part in the design flow of integrated circuits, helping circuit designers to verify the functionality and performance of their designs without going through expensive fabrication processes. As the semiconductor processing technology migrates to nanometer dimensions, new simulation methodologies are needed to solve the new problems intrinsically existing in circuit design with nanometer features. Modern integrated circuits continually challenge circuit simulation algorithms and implementations in the development of new technology generations. The semiconductor industry requires EDA software with the ability to analyze nanometer effects like coupling noise, ground bounce, transmission line wave propagation, dynamic leakage current, supply voltage drop, and nonlinear device and circuit behavior, which are all related to dynamic current. Thus, detailed circuit simulation and transistor-level simulation have become one of the most effective ways to investigate and resolve issues with nanometer designs.
Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE. SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators, or SPICE. The SPICE method considers a circuit as a non-divided object.
SPICE-like simulations may provide fairly accurate predictions of how corresponding circuits will behave when actually built. The predictions are preferably made not only for individual sub-circuit but also for whole systems (e.g., whole integrated circuits) so that system-wide problems relating to noise and the like may be uncovered and dealt with. In a general process flow of a SPICE-like simulation, an analog integrated circuit under simulation is often represented in the form of a netlist description. A netlist is a circuit description of the analog circuit to be simulated written in a SPICE-like language. SPICE netlists are pure structural languages with simulation control statements. Other language like Verilog-A™ has the capability to include behavioral constructs. The structural netlist of SPICE together with a predefined set of circuit components of the analog integrated circuit may be represented in the form of a matrix in accordance with certain circuit modeling methodologies. The number of non-linear differential equations ranges from 1 to n. There are a corresponding number of input vectors to be operated by the linear equation. The set of input vectors are shown as {I1, I2, . . . In}. Next, the linear matrix is computed with the set of input vectors to generate a set of solution vectors {V1, V2, . . . Vn}. The computation is repeated until the set of solutions converge. The set of solutions may be then displayed in the form of waveforms, measurements, or checks on a computer screen for engineers to inspect the simulation results.
However, SPICE-like simulation of a whole system becomes more difficult and problematic as the industry continues its relentless trek of scaling down to smaller and smaller device geometries and of cramming more interconnected components into the system. An example of such down scaling is the recent shift from micron-sized channels toward deep submicron sized transistor channel lengths. Because of the smaller device geometries, a circuit designer are able to cram exponentially larger numbers of circuit components (e.g., transistors, diodes, capacitors) into a given integrated circuit (IC), and therefore increases the matrix size to a complexity which may not be solved in a desired time frame.
A circuit may be represented as a large numerically discrete nonlinear matrix for analyzing instant current. The matrix dimension is of the same order as the number of the nodes in the circuit. For transient analysis, this giant nonlinear system needs to solve hundreds of thousand times, thus restricting the capacity and performance of the SPICE method. The SPICE method in general can simulate a circuit up to about 50,000 nodes. Therefore it is not practical to use the SPICE method in full chip design. It is widely used in cell design, library building, and accuracy verification.
With some accuracy lost, the Fast SPICE method developed in the early 1990s provides capacity and speed about two orders of magnitude greater than the SPICE method. The performance gain was made by employing simplified models, circuit partition methods, and event-driven algorithms, and by taking advantage of circuit latency.
SPICE models a circuit in a node/element fashion, i.e., the circuit is regarded as a collection of various circuit elements connected at nodes. At the heart of SPICE is the so-called Nodal Analysis, which is accomplished by formulating nodal equations (or circuit equations) in matrix format to represent the circuit and by solving these nodal equations. The circuit elements are modeled by device models, which produce model results that are represented in the circuit equations as matrices.
A device model for modeling a circuit element, such as the SPICE model for modeling MOSFET devices, developed by UC Berkeley, typically includes model equations and a set of model parameters that mathematically represent characteristics of the circuit element under various bias conditions. For example, a circuit element with n terminals can be modeled by the following current-voltage relations:Ii=fi(V1, . . . ,Vn,t) for i=1, . . . ,n, where Ii represents the current entering terminal I; Vj (j=1, . . . , n) represents the voltage or terminal bias across terminal j and a reference terminal, such as the ground; and t represents the time. The Kirchhoff's Current Law implies that the current entering terminal n is given by
      I    n    =            ∑              i        =        1                    n        -        1              ⁢                  I        i            .      A conductance matrix of the circuit element is defined by:
      G    ⁡          (                                                  V                              1                ,                                                                        …              ⁢                                                          ,                                                                          V                n                            ,                                            t                              )        :=            (                                                                  ∂                                  f                  1                                                            ∂                                  V                  1                                                                          …                                                              ∂                                  f                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋱                                ⋮                                                                              ∂                                  f                  n                                                            ∂                                  V                  1                                                                          …                                                              ∂                                  f                  n                                                            ∂                                  V                  n                                                                        )        .  To model the circuit element under alternating current (AC) operations, the device model also considers the relationship between node charges and the terminal biases:Qi=qi(V1, . . . ,Vn,t) for i=1, . . . ,n. where Qi represents the node charge at terminal i. Thus, the capacitance matrix of the n-terminal circuit element is defined by
      C    ⁡          (                                                  V                              1                ,                                                                        …              ⁢                                                          ,                                                                          V                n                            ,                                            t                              )        :=            (                                                                  ∂                                  q                  1                                                            ∂                                  V                  1                                                                          …                                                              ∂                                  q                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋱                                ⋮                                                                              ∂                                  q                  n                                                            ∂                                  V                  1                                                                          …                                                              ∂                                  q                  n                                                            ∂                                  V                  n                                                                        )        .  
FIG. 1A illustrates a conventional method of determining a yield of a circuit in semiconductor manufacturing. As shown in FIG. 1A, Monte Carlo SPICE simulation is often used for circuit design with process corners. For circuits with high replication counts of cells, such as SRAM 102, the probability of failure (Pf) is required to be very low such that the overall probability of failure of an integrated circuit (also referred to as a chip) that includes the SRAM 102 can be low. For example, for a SRAM 102 having one million cells 104, the probability of failure needs to be in the order of 1e-8 to achieve a chip failure rate of less than one percent. To ensure high yields, i.e., low probability of failure, a large number of Monte Carlo samples, such as 1e-8 samples, may be simulated in order to predict a probability of failure of 1e-8. However, simulating such a large Monte Carlo samples consumes a long time and lots of resources. In addition, for high sigma Monte Carlo simulations, the conventional method tends to simulate too many samples in the low sigma region, and simulate too few samples in the high sigma region.
Therefore, there is a need for methods and systems that address the issues of the conventional method of yield prediction described above.